Write the code to compare two 8-bit buses, a and b. The output signal is agrb...

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Electrical Engineering

Write the code to compare two 8-bit buses, a and b. The outputsignal is agrb for â€œa greater than b.â€

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4.1 Ratings (821 Votes)

-----------the VHDL code for your design is--------------

---------VHDL CODE-------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity compare_8bit is
Â Â Â Â port(
Â Â Â Â Â Â Â Â a : in STD_LOGIC_VECTOR(7 downto 0);
Â Â Â Â Â Â Â Â b : in STD_LOGIC_VECTOR(7 downto 0);
Â Â Â Â Â Â Â
Â Â Â Â Â Â Â Â agrb : out STD_LOGIC
Â Â Â Â Â Â Â
Â Â Â Â Â Â Â Â );
end compare_8bit;

architecture Behavioural of compare_8bit is
begin

agrb<= '1' when (a>b) else
Â Â Â Â Â Â Â Â Â Â Â Â Â Â '0';

end Behavioural;

////////the verilog module for your design is ////////////////

module compare_8_bit (a,b,agrb);///declare the inputs and output
input [7:0] a,b;
output agrb;Â Â Â ///output signal Q (Q3Q2Q1Q0)

assign agrb=(a>b)?1:0;///?-is ternaery operator compares a,b
Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â //ifa>b then agrb signal equal to 1 otherwise 0
endmodule

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