The objective of this lab is to practice your Verilog coding andthe design of a Finite State Machine. Lab Goal: For this lab, youwill code a Verilog module to implement the FSM described in thisdocument. This lab will also require that you use the Seven -Segment Display on the DE0 - CV FPGA board. Design Specificationsfor the FSM Implem ent the following simple state machine on theDE0 - CV FPGA board. This FSM will have 5 states. The clock to thisFSM will be provided by yourself using KEY0 (one of the pushbuttons on the board). Include a debounce module in your code butdo not use it. S o you write the code as described in the lecture,but there should be no debounce module instance. I want you tounderstand this module but it is unnecessary on our board. Thetransitions from any one state to another are determined byswitches 0 through 4 of the board (SW0, SW1, SW2, SW3, and SW4) asshown in the state diagram below. This will be easier than usingpushbuttons for the inputs to switch to states. That means you setthe switch and then clock it using KEY0. It really only matterswhat the swi t ch positions are when the clock edge occurs. NOTEreiterating this use slide s witches not pushbuttons for input. UseKEY0 for the clock, and generate the clock signal by hand bypushing KEY0. Any input transition not explicitly referenced in thediagram keeps the machine in the same state. Moreover, if two ormore switches are asserted simultaneous ly, no transition shouldoccur. SW0 acts as the rese t and should reset the FSM to S 00regardless of all other switches or the pushbutton. (note you coulduse K EY1 pushbutton instead but it isn’t clear that would bebetter). How to write your code: Study Lecture 9 section 3 on howto write a Finite State Machine in Verilog. Your code will have twoparts. There will be a synchronous part which is the part modelsthe flip flops. An example of this is Lecture 9 slide 33. The otherpart is the combinatorial part, which is the part that feeds theinputs to the flip flops, that is like the code in Lecture 9 slides29 through 32. This i
