A T flip-flop is a 1-bit synchronous storage component alternative to the D flip-flop, with a...

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Electrical Engineering

A T flip-flop is a 1-bit synchronous storage componentalternative to the D flip-flop, with a slightly differentinterface. The T flip-flop has one input t tosynchronously control the state of the flip-flop, as follows:
When t is 0, the flip-flop does not change itsstate value.
When t is 1, the flip-flop inverts its currentstate value (0 becomes 1, and 1 becomes 0).
Write a Verilog module for the T flip-flop using a behavioralmodel. The flip-flop should be triggered by the rising edge of theclock input. It should also have an asynchronous active-low resetinput to reset the flip-flop state to zero

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4.3 Ratings (923 Votes)

////VERILOG HDL FOR THE T-flipflop with asynchronous reset active high input//////////////

module T_ff(T,RST,CLK,Q,Q_bar);
input RST,T,CLK;
output Q,Q_bar;

reg Q,Q_bar;Â Â //consider two variable signals
initialÂ Â Â Â Â Â Â //assign a reset state to the flipflop initially(its notÂ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â mandatory)
Â Â Â begin
Â Â Â Â Â Q<=1'b0;
Â Â Â Â Â Q_bar<=1'b1;
Â Â Â end
always@(posedge CLK or posedge RST)//responds when clock raising edge or RESET raising edge is occurred.
begin
Â Â Â if(RST==1'b1) begin //Check wheather reset is pressed or not
Â Â Â Â Â Â Â Â Q<=1'b0;
Â Â Â Â Â Â Â Â Q_bar<=1'b1;
Â Â Â Â Â Â end
Â Â Â Â Â else begin
Â Â Â Â Â Â Â if(T==1'b0) begin //if T=0 Then assign previous state to the flipflop out put
Â Â Â Â Â Â Â Â Q<=Q;
Â Â Â Â Â Â Â Â Q_bar=Q_bar;
Â Â Â Â Â Â Â end
Â Â Â Â else beginÂ Â //if T=1 then Togle the state it have prevously
Â Â Â Â Â Â Â Q<=~Q;
Â Â Â Â Â Â Â Q<=~Q_bar;
Â Â Â Â Â end
Â Â Â Â end
Â Â end
endmodule

(if you have any query leave a comment. Thank you)

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