Write down the VERILOG code for an XOR gate and the testbench code to test it

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Electrical Engineering

Write down the VERILOG code for an XOR gate and the testbench codeto test it

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XOR GATE

Verilog design

//in Structural model

module xor_gate (
input a,b,
output y);

Â Â Â xor x1(y,a, b);

endmodule

TestBench

module tb_and_gate;

Â Â Â Â reg A,B;
Â Â Â Â wire Y;
Â Â Â Â
Â Â Â Â xor_gate a1 (.a(A) ,.b(B),.y(Y));Â Â Â Â Â Â Â Â Â
Â Â Â Â
Â Â Â Â initial begin
Â Â Â Â
Â Â Â Â Â Â Â Â A =1'b0;
Â Â Â Â Â Â Â Â B= 1'b0;
Â Â Â Â Â Â Â Â #45 $finish;
Â Â Â Â
Â Â Â Â endÂ Â Â Â Â
Â Â Â Â
Â Â Â Â always #6 A =~A;
Â Â Â Â always #3 B =~B;
Â Â Â Â
Â Â Â Â always @(Y)
Â Â Â Â $display( \"time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value Y =%b\",$time,A,B,Y);

endmodule

output

time =0Â Â Â Â Â Â Â Â INPUT VALUES:Â Â Â Â A=0 B =0Â Â Â Â Â Â Â Â output value Y =0
time =3Â Â Â Â Â Â Â Â INPUT VALUES:Â Â Â Â A=0 B =1Â Â Â Â Â Â Â Â output value Y =1
time =6Â Â Â Â Â Â Â Â INPUT VALUES:Â Â Â Â A=1 B =0Â Â Â Â Â Â Â Â output value Y =1
time =9Â Â Â Â Â Â Â Â INPUT VALUES:Â Â Â Â A=1 B =1Â Â Â Â Â Â Â Â output value Y =0

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