We want to design a simple \"four clock pulse\" timer circuit. Inaddition to the clock input, the timer has a \"Restart\" input (R),three \"data\" outputs (ABC) which indicate the count, and one\"beeper\" output (D). The behavior of the circuit is as follows:

Idle Mode The timer output is ABC=100 and thebeeper is off (D=0) as long as R=0. If R=1 on any clock edge inthis mode, the timer goes into the...

Restart/Hold Mode The timer output is ABC=000 andthe beeper is off (D=0) as long as R=1. If R=0 on any clock edge inthis mode, the timer goes into the...

Counting Mode Provided that the counter is notrestarted (i.e. provided that R=0), the timer goes through thesequence of data and beeper outputs shown below (one full clockpulse each) and then returns to the Idle mode. If R=1 on any clockedge in this mode, the timer goes into the Restart/Hold mode.

A	B	C	D
0	0	0	0
0	0	1	0
0	1	0	0
0	1	1	0
1	0	0	1

Use D-flops, AND gates, OR gates, and inverters to design aMoore machine that performs this function. No more than 3 D-typeflip-flops should be used. Carry out your solution as follows:

(a) How many states does this timer have? Make a list of thesestates, giving each a label and a verbal description. How many bitsare required to specify all states? Name the state bits and assignvalues to each for every state.

(b) Construct a complete state table for this machine, includingall inputs, outputs, and states. Include any don't-careconditions.

(c) Construct a state diagram for this machine.

(d) How many signals must be generated by combinational logicfor this machine? What are they? Use Karnaugh maps to obtainminimized Boolean expressions for these signals.

(e) Draw a complete circuit diagram for your state machine,showing all inputs and outputs, flip-flops, combinational circuits,and interconnects.