We assume a superscalar pipeline capable of fetching and
decoding two instructions at a time, having...
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We assume a superscalar pipeline capable of fetching anddecoding two instructions at a time, having two separate functionalunits (e.g., one integer arithmetic and one floating-pointarithmetic), and having two instances of the write-back pipelinestage. Assume the following constraints on a six-instruction codefragment:
Inst-1 is a floating point operation
Inst-2 requires two cycles to execute and depends on output ofInst-1
Inst-3 and Inst-4 conflict for the same functional unit. Inst-3and Inst-4 are floating point operations.
Inst-5 is an Integer operation
Inst-5 and Inst-6 conflict for a functional unit.
Integer operations can be performed on integer or floating pointunit whichever found available but floating point operations mustrequire floating point unit.
Show the states of different stages of superscalar processor atdifferent clock cycles for any instruction issue policy. Pleasemention the policy you use to answer the question.
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