Verilog counter problem:

Using the attached 4-bit up-counter module and testbench as atemplate, write a Verilog module that implements a certain 4-bitcounter. The module should include two more input variables:“updown” and “count2”.

If “updown” is 1, the circuit should count up (by 1s); if it is0 it should count down (by 1s).

If “count2” has a value of 1, the circuit should instead countup by 2s; otherwise it will have no effect (the circuit countsnormally up or down by 1s).

(Hint: use “if” and “else if” statements. After checking the“Resetn” value, check the value of “count2”).

Simulate the module in EDA Playground. In the testbench, use thefollowing input signals:

    Clock =0;                      // initial value

    updown =1;                 // initially count up

    count2 =0;                   // count-by-2 disabled

    Resetn =0;                   // reset active

    En =1;                                          // enable active

    #10

    Resetn =1;                   // reset disabled

    #40

    updown =0;                 // count down

    #80

    count2 =1;                   // count-up-by-2 enabled

    #40

Submit a printout your module (do not have to show thetestbench) as well as a screenshot of the simulation results(waveforms