Using the programing language of Verilog I attempted to make acounter to count from 0 to 9 then loop back to 0 using the internalclock of the FPGA cyclone IV from altera. the code is posted at thebottom
I get the following errors
Error (10663): Verilog HDL Port Connection error atEncryption.v(9): output or inout port \"clk\" must be connected to astructural net expression
Error (10285): Verilog HDL Module Instantiation error atEncryption.v(9): instance \"\" specifies 3 actual port connectionsbut module \"clockgen\" only expects 2
Error (12153): Can't elaborate top-level user hierarchy
Can someone help me debug this code so it can count upto 9
module Encryption(SW, CLOCK_50, OUT, HEX0);
input[1:0]SW;
input CLOCK_50;
output reg[6:0] HEX0;
output [3:0]OUT;
wire S1, S2, S3;
clockgen(CLOCK_50, 25000000,clk);
Tflipflop(SW[0], clk, SW[1], OUT[0]);
and(S1, clk, SW[0], OUT[0]);
Tflipflop(S1, clk, SW[1], OUT[1]);
and(S2, S1, OUT[1]);
Tflipflop(S2, clk, SW[1], OUT[2]);
and (S3, S2, OUT[2]);
Tflipflop(S3, clk, SW[1], OUT[3]);
always
begin
case(OUT)
4'b0000: HEX0 = 7'b1000000;
4'b0001: HEX0 = 7'b1111001;
4'b0010: HEX0 = 7'b0100100;
4'b0011: HEX0 = 7'b0110000;
4'b0100: HEX0 = 7'b0011001;
4'b0101: HEX0 = 7'b0010010;
4'b0110: HEX0 = 7'b0000010;
4'b0111: HEX0 = 7'b1111000;
4'b1000: HEX0 = 7'b0100000;
4'b1001: HEX0 = 7'b0010000;
4'b1010: HEX0 = 7'b0001000;
4'b1011: HEX0 = 7'b0000011;
4'b1100: HEX0 = 7'b1000110;
4'b1101: HEX0 = 7'b0100001;
4'b1110: HEX0 = 7'b0000110;
4'b1111: HEX0 = 7'b1001110;
endcase
end
endmodule
module Tflipflop(En, Clk, Clear, Q);
output Q;
input En, Clk, Clear;
reg Q;
always @(posedge Clk)
if (Clear == 0)
begin
Q = 1'b0;
end
else
begin
Q = En^Q;
end
endmodule
module clockgen(clk_in, clk_out);
input clk_in;
output[3:0] clk_out;// count up to 9 length must be 4 so[3:0]
reg[3:0] counter = 0; //temp variable
always@(posedge clk_in)
begin
if(counter< 9)
counter<=counter+1;//manupulate temp variable
else
counter = 0;
end
assign clk_out = counter;//assigning temp variable value(counterin always block) to the output variable
endmodule
