Using the following VHDL code for an 8 bit adder, make the sumbe displayed on the seven segment display of an Elbert V2 Spartan3A FPGA Board.

VHDL:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity state_bit_adder is

Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
           D : inSTD_LOGIC;
           Enable : outSTD_LOGIC_vector (2 downto 0);
           input: instd_logic_vector(7 downto 0);
           SUM: outstd_logic_vector(8 downto 0));
          
end state_bit_adder;

architecture Behavioral of state_bit_adder is
type statetype is (start, secondstate);
signal state, nextstate: statetype;

signal tempsum1, tempsum: STD_LOGIC_VECTOR (8 downto 0);

begin
Enable <= \"110\";
process(clk, reset)
begin
if(reset ='0') then
state <= start;
elsif rising_edge(clk) then
state <= nextstate;
end if;
end process;

process(state, input, D)
begin
case (state) is
when start =>
tempsum1 <= ('0'&input);
if (D = '0') then
nextstate <= secondstate;
end if;

when secondstate =>
tempsum <= ('0'&input);
if (D = '0') then
nextstate <= start;
end if;
end case;
end process;

SUM <= tempsum1 + tempsum;

End Behavioral;

Constraint File:

###Clock
NET \"clk\" LOC = P129 | IOSTANDARD = LVTTL | PERIOD = 12 MHz;
NET \"D\" CLOCK_DEDICATED_ROUTE = FALSE;
############Input push buttons
NET \"reset\" LOC = P80 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW =FAST | PULLUP;
NET \"D\" LOC = P79 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST |PULLUP;

###########output LED
NET \"SUM[7]\" LOC = P46 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =FAST;
NET \"SUM[6]\" LOC = P47 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =FAST;
NET \"SUM[5]\" LOC = P48 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =FAST;
NET \"SUM[4]\" LOC = P49 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =FAST;
NET \"SUM[3]\" LOC = P50 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =FAST;
NET \"SUM[2]\" LOC = P51 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =FAST;
NET \"SUM[1]\" LOC = P54 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =FAST;
NET \"SUM[0]\" LOC = P55 | IOSTANDARD = LVTTL | DRIVE = 8;#| SLEW =FAST;
     
   NET \"SUM[8]\" LOC = P117 | IOSTANDARD = LVTTL | SLEW =SLOW | DRIVE = 12;
     
   NET \"Enable[0]\" LOC = P120 | IOSTANDARD = LVTTL | SLEW= SLOW | DRIVE = 12;
   NET \"Enable[1]\" LOC = P121 | IOSTANDARD = LVTTL |DRIVE = 8;
   NET \"Enable[2]\" LOC = P124 | IOSTANDARD = LVTTL |DRIVE = 8;

     
     
#####################################################################################################
## DP Switches
#####################################################################################################

NET \"input[0]\" LOC = P70 | PULLUP | IOSTANDARD = LVTTL | SLEW =FAST | DRIVE = 8;
NET \"input[1]\" LOC = P69 | PULLUP | IOSTANDARD = LVTTL | SLEW =FAST | DRIVE = 8;
NET \"input[2]\" LOC = P68 | PULLUP | IOSTANDARD = LVTTL | SLEW =FAST | DRIVE = 8;
NET \"input[3]\" LOC = P64 | PULLUP | IOSTANDARD = LVTTL | SLEW =FAST | DRIVE = 8;
NET \"input[4]\" LOC = P63 | PULLUP | IOSTANDARD = LVTTL | SLEW =FAST | DRIVE = 8;
NET \"input[5]\" LOC = P60 | PULLUP | IOSTANDARD = LVTTL | SLEW =FAST | DRIVE = 8;
NET \"input[6]\" LOC = P59 | PULLUP | IOSTANDARD = LVTTL | SLEW =FAST | DRIVE = 8;
NET \"input[7]\" LOC = P58 | PULLUP | IOSTANDARD = LVTTL | SLEW =FAST | DRIVE = 8;