- Using behavioral VHDL, design a Moore-typefinite state machine that detects input test vector that containsthe sequence of ‘100’. If the sequence ‘100’ is detected, theoutput Z should go high. The input is to be named W, the output isto be named Z, a Clock input is to be used and an active low resetsignal (Resetn) should asynchronously reset the machine.
a) Draw the Moore-type model statediagram for the FSM.
b) Write the VHDL code to implementthe FSM.
