module traffic(a, b,clk, reset, P1, P2, PL1, PL2, ind);
input a,b;
input clk; //g=100 y=010 r=001
input reset; //g for pedes = 000 red = 111
input ind;
output[2:0] P1;
output[2:0] P2; // two roads
output[1:0] PL1; //Pl is pedestrian
output[1:0] PL2;
reg [2:0] P1;
reg [2:0] P2;
reg [1:0] PL1;
reg [1:0] PL2;
reg [2:0] sig;
always @(posedge clk, posedge reset)
if(reset)
begin
P1 <= 3'b100;
P2 <= 3'b001;
PL1 <= 3'b111;
PL2 <= 3'b000;
end
else begin
// pass the next_state to current_state;
sig <= sig + 1;
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case(sig[2:0])
3'b000:begin
P1 <= 3'b100; //path 1 is greeen
P2 <= 3'b001; //path 2 is red
PL1 <= 3'b111;
PL2 <= 3'b000;
end
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3'b001:begin
P1 <= 3'b010; //path 1 is yellow
P2 <= 3'b001; // path 2 is red
PL1 <= 3'b000;
PL2 <= 3'b111;
end
3'b010:begin
P1 <= 3'b001; //path 1 is red
P2 <= 3'b100; //path 2 is green
PL1 <= 3'b000;
PL2 <= 3'b111;
end
3'b011:begin
P1 <= 5'b001; //path 1 is red
P2 <= 5'b010; //path 2 is yellow
PL1 <= 3'b000;
PL2 <= 3'b111;
end
3'b100:begin
P1 <= 3'b001; //path 1 is red
P2 <= 3'b001; //path 3 is red
PL1 <= 3'b000;
PL2 <= 3'b000;
end
5'b11111:sig<= 6'b00000;
default:begin  Â
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end
endcase
end
endmodule
Can anyone write a testbench for this in Verilog, ind meansindicator.
