LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Vendingvhdl IS PORT( Clk                            : IN        STD_LOGIC; Change                    : OUT    STD_LOGIC_VECTOR(1 downto 0); Inputs                      : IN        STD_LOGIC_VECTOR(1 downto 0); output                     : OUT   ...

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Question

Electrical Engineering

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY Vendingvhdl IS

PORT(

Clk                           : IN        STD_LOGIC;

Change                   : OUT    STD_LOGIC_VECTOR(1 downto 0);

Inputs                     : IN        STD_LOGIC_VECTOR(1downto 0);

output                    : OUT    STD_LOGIC);

END Vendingvhdl;

ARCHITECTURE vending of Vendingvhdl IS

                             TYPE STATE_TYPE IS (empty, fivecent, tencent, ready);

                             SIGNAL current_state, next_state   : STATE_TYPE;

BEGIN

Combinational LOGIC

COMBINE: PROCESS (inputs)

BEGIN

                             CASE current_state IS

                                            When empty =>

                                                           IF inputs = “00” THEN

                                                                                         next_state <= empty;

                                                                                         output <= ‘0’;

                                                                                         change <= “00”;

                                                           ELSEIF inputs = “01” THEN

next_state <= fivecent;

                                                                                         output <= ‘0’;

                                                                                         change <= “00”;

ELSEIF inputs = “10” THEN

next_state <= tencent;

                                                                                         output <= ‘0’;

                                                                                        change <= “00”;

ELSEIF inputs = “11” THEN

next_state <= ready;

                                                                                         output <= ‘1’;

                                                                                         change <= “10”;

                                                           ENDIF;

                                            WHEN fivecent =>

                                                           IF inputs = “00” THEN

next_state <= fivecent;

                                                                                         output <= ‘0’;

                                                                                         change <= “00”;

ELSEIF inputs = “01” THEN

next_state <= tencent;

                                                                                         output <= ‘0’;

                                                                                         change <= “00”;

ELSEIF inputs = “10” THEN

next_state <= ready;

                                                                                         output <= ‘0’;

                                                                                         change <= “00”;

ELSEIF inputs = “11” THEN

next_state <= ready;

                                                                                         output <= ‘1’;

                                                                                         change <= “01”;

                                                                                        change <= “10”;

                                                           ENDIF;

                                            WHEN tencent =>

                                                           IF inputs = “00” THEN

next_state <= tencent;

                                                                                         output <= ‘0’;

                                                                                         change <= “00”;

ELSEIF inputs = “01” THEN

next_state <= ready;

                                                                                         output <= ‘1’;

                                                                                         change <= “00”;

ELSEIF inputs = “10” THEN

next_state <= ready;

                                                                                         output <= ‘1’;

                                                                                         change <= “00”;

ELSEIF inputs = “11” THEN

next_state <= ready;

                                                                                         output <= ‘1’;

                                                                                         change <= “01”;

                                                                                         change <= “10”;

Please complete the following VHDL code...I am implementing asimple vending machine FSM

Answer & Explanation Solved by verified expert
4.3 Ratings (538 Votes)
Here it is understood from code snipet that cost of good is15 cent Hence two more states added to return    See Answer
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