It is required to design a synchronous sequential circuit that receives two input bit streams X...

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Electrical Engineering

It is required to design a synchronous sequential circuit thatreceives two input bit streams X and Y, and detects identical 4-bitsequences in both X and Y that are non-overlapping. The output Z isalso a bit stream that produces a 1 only after detecting twoidentical 4-bit input sequences. Use an asynchronous reset input toreset the sequential circuit to its initial state.
Example:
X: 001010 110010 0111 1010100 0111
Y: 011010 100010 0111 1000100 0010
Z: 000001 000001 0001 0000001 0000
a) (5 points) Draw a Mealy state diagram of the sequentialcircuit.
b) (10 points) Implement your design using a minimal number ofD-type flip flops and combinational logic. Show the K-maps andwrite the minimal next state and output equations. Draw the circuitdiagram.
c) (10 points) Write a structural Verilog model that models yourimplemented sequential circuit by modeling the D Flip-Flops andinstantiating them and modeling the combinational part using eitherassign statement or gate primitives.
d) (10 points) Write a test bench that tests your structuralVerilog model in (c) using the given input sequence. Start byresetting all flip-flops and then apply the input sequences of Xand Y shown above. Verify that your circuit produces the correctoutput by including the generated waveform from simulation.
e) (10 points) Write a behavioral Verilog description that modelsyour state diagram in part (a).
f) (5 points) Write a test bench that tests your behavioral Verilogmodel of part (e). Start by resetting all flip-flops and then applythe input sequences of X and Y shown above. Verify that yourcircuit produces the correct output by including the generatedwaveform from simulation.
g) Submit a report (Word or PDF document) that shouldcontain:
i. The state diagram of your design (part a).
ii. The K-maps, equations, and circuit diagram of your sequentialcircuit (part b).
iii. A copy of the Verilog modules and test benches of parts (c) to(f)
iv. The timing diagrams (waveforms) taken directly as snapshotsfrom the simulator for
parts (d) and (f).
Take All the time you need.

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