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I need a synthesizable Verilog code/module implementing the IEEE 754 Floating Point multiplication and a corresponding...

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Electrical Engineering

I need a synthesizable Verilog code/module implementing the IEEE754 Floating Point multiplication and a corresponding test bench.It should set a flag for underflow and overflow conditions if theyarise during the multiplication for the output. It would be greatlyappreciated if someone could write this floating pointmultiplication code in Verilog with some comment lines so i couldunderstand the functioning too with a test bench module ! I havetried to explain everything as clearly as possible and really hopesomeone can help me out here !

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