HI can I please know whats wrong in this 2to1 mux code in VHDLcode

also please type it out so theres no confusion thank you

-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
-- entity declaration for testbench
entity test mux2 is
end test;
--architecture Body declaration for 2to1 mux
-- component declaration of source entity 2to1 mux
component test mux2 is
port (
sel : in std_logic ; --select input,
A : in std_logic ; --data input
B : in std_logic ;--data input
y : out std_logic ); -- mux output
end component;

--internal Signal declarations
singal sel: std_logic;
singal A,B: std_logic;
singal y: std_logic;
begin

--Instantiate Device under test (out) of 2to1 mux
OUT: test mux2
port map (
sel => sel,
A => A,
B => B,
y => y);

--stimulus process
process
begin
sel <= '0'; A <= '0'; B <= '0';
wait for 10 ns;
sel <= '0'; A <= '0'; B <= '1';
wait for 10 ns;
sel <= '0'; A <= '1'; B <= '0';
wait for 10 ns;
sel <= '0'; A <= '1'; B <= '1';
wait for 10 ns;
sel <= '1'; A <= '0'; B <= '0';
wait for 10 ns;
sel <= '1'; A <= '0'; B <= '1';
wait for 10 ns;
sel <= '1'; A <= '1'; B <= '0';
wait for 10 ns;
sel <= '1'; A <= '1'; B <= '1';
wait;
end process;

DESIGN CODE
library IEEE;
use IEEE.std_logic_1164.all;
-- entity declaration for 2-to-1 mux
entity test mux2 is
port (
sel : in std_logic ; --select input,
A : in std_logic ; --data input
B : in std_logic ;--data input
y : out std_logic); -- mux output
end mux2;

--architecture Body declaration for 2to1 mux
architecture Behavioral of test mux2 is
begin
y <= (((not sel) and A) or (sel and B));
end Behavioral;