Directions: Let’s look at how pipelined executecan be affected by resource hazards, control hazards andinstruction set architecture. Looking at the following fragment ofcode:
ADD X5, X2, x1
LDUR X3, [X5, #4]
LDUR X2, [X2, #0]
ORR X3, X5, X3
STUR X3 [X5, #0]

Assume that all of the branches are perfectly predicted as thiseliminates all potential control hazards and that no delay slotswill be needed. If we only have one memory for both theinstructions and data, there is a structural hazard every time thatwe need to fetch an instruction in the same cycle which anotherinstruction accesses data. To guarantee that we have forwardprogress, this structural hazard has to be resolved by giving thefavor to the instruction that accesses data.

What would be the total execution time of the sequence in the5-stage pipeline that only has one memory? Explain your answer.

Assume now that all the branches are perfectly predicted as thiseliminates all potential control hazards and that no delay slotswill be needed. If we change the load/store instructions to use aregister without an offset as the addresses, the instructions wouldno longer need to use the ALU. As a result, the MEM and EX stagescan be overlapped and the pipeline would only now have 4stages.

Change the code to accommodate the changed ISA. What is thespeedup achieved in this instruction sequence? Explain youranswer.

Show a pipeline execution diagram for these series ofinstructions (both initial and end) result.

Please answer the questions accordingly there are three ofthem.

Please make copy paste available