Design Task 2: One Second Prescalar In many systems it isdesirable to have a very fast system clock to clock most of thesequential entities in the system. However, there may be othersequential entities in the same system that need to be clocked at amuch slower speed. An approach that allows flexibility ingenerating a slower clock frequency is a frequency divider, alsocalled a prescalar. This is basically a counter that generates apulse every n cycles of its input clock. The output occurs as apulse with a frequency that is 1/n of the input clock frequency.However, the output pulse has a fixed duration that is one clkperiod long. 4 The prescalar to be designed is namedone_sec_prescalar. If its cnt_en input is asserted at a rate of32.768 kHz it must generate an output pulse every second. So, thisdesign divides down it input by 32768. The input pulse is onesystem clock in duration and output pulse is one system clock induration. This entity must also generate an output named one_hzthat is a 1Hz square wave. The entity declaration for the onesecond prescalar is:

entity one_sec_prescalar is port( clk : in std_logic; -- systemclock

rst_n : in std_logic; -- active low synchronous reset

clr_n : in std_logic; -- synchronous clear

cnt_en : in std_logic; -- count enable

one_hz : out std_logic; -- one Hz square wave output

one_sec_tick : out std_logic -- one clock wide pulse every sec);