Design a clocked synchronous state machine with two inputs, A and B, and a single output Z that is 1 if(1) A had the “different†value at each of the two previous clock ticks, or(2) B has been 1 since the last time that the first condition was true.Otherwise, the output should be 0.Design state assignment using decomposed method. D Use flip-flops to a minimum, and design the next-state logic with a minimal 2-level NAND-NAND circuit. Do not consider multiple-output minimization when designing next-state logic.
