Design a 4-bit up/down counter which displays its output on thethe 7-led segment using the decoder used in Lab 2.

In this lab, you will design a 4-bit up/down counter whichdisplays its output on the 7-segment LED using the decoder that youdesigned in Lab 2.
The 4-bit up/down counter module has 4 inputs, Clk_1Hz, Reset,Pause, and Up; and a 4-bit output Count. If Reset is 1, the countershould reset its count value to zero (0000). If Reset is 0 andPause is 1, the counter should pause and continue displaying thecurrent count value. Otherwise, if Up is 1, on every clock cyclethe counter should count up by one number. If Up is 0, the countershould count down on every clock cycle.
Upon reaching the minimum (0000) or maximum (1011) count, thecounter value should wraparound. For example, when counting up, thecounter should wraparound to 0000 after 1011, and when countingdown, the counter should wraparound to 1011 after 0000. Reset haspriority over Pause, which in turn has priority over counting up ordown.
As in Lab 2, the left 8 switches should control which digits are onor off. This time, the rightmost switch will connect to Up; yourcounter should count up if this switch is up, and down if thisswitch is down. Connect BTNL to Pause, BTNR to Reset, and BTND toClkDiv_Reset (the reset input to the ClkDiv module).
Lab Procedure and Demo: 1. Behaviorally design the 4-bit Up/DownCounter to operate as specified in the Lab Overview above. This isa behavioral design, not a structural design, so you may useif/else or case statements or any other Verilog statement that youwant in the Counter module. You can read about these statements inchapter 6 of Verilog for Digital Design. You will also need tocreate your own Counter_Top module. You may modify any of thedownloaded files or your own 7-segment display module as desired.2. Create a testbench to test your design for correctfunctionality. At a minimum, the testbench should test thefollowing cases: a. Check that counter counts up then downcorrectly b. Check for correct wraparound functionality forcounting up and down c. Check for correct reset behavior fromnon-one count value d. Check for correct pause behavior e. Checkthat Reset has priority over Pause Your testbench module does notneed to generate Tcl Console outputs; your simulation only needs togenerate waveforms for this lab. You do not need to include theClkDiv1Hz or Counter4_Top modules when you simulate a response withyour testbench program. You do need to generate a signal for theclock input to your counter module. 3. Modify“Nexys4DDR_Master.xdc” as in Lab 2 to enable all 16 switches, andall 8 seven-segment displays on the FPGA board. Also, uncomment thetwo lines under the “## Clock signal” heading, and the lines forBTNL, BTNR, and BTND under the “##Buttons” heading. Synthesize,download and test your design on the Nexys4 FPGA board for correctfunctionality. At a minimum, you should test the same cases as yourtestbench. Demonstrate the correct behavior to your instructor. Asin Lab 2, it may be easier to do this step before step 2.