Design a 3-bit 2’s complement adder/subtractor withoverflow flag detection

Design and simulate a structural model (notbehavioral) of a 3-bit Adder/Subtractor). Use the 3-bit carrypropagate adder of the project as a module for youradder/subtractor. The inputs A andB should be positive binary numbers where vectorB must be converted to a negative 2's complementwhen a subtraction operation is configured. When m=0 it shouldperform and addition (A+B) and if m=1 it shouldperform a subtraction operation (A-B)

Your module ports (inputs and outputs), should be as follow:

module add_sub(

   input [2:0] a, b,

   input m,   // m=0 =>addition (a+b);   m=1 => subtraction(a-b)

   output [2:0]result,  

   output overflow

);

/* your wire declarations, n-bit adder and xorgates

go in this section */

endmodule

Create a test bench to test the following 2’s complementcases:

a = 3’b001 b = 3’b001 m = 1’b0     //(1+1=2) => result = 3’b010;  overflow = 1’b0

a = 3’b011 b = 3’b010 m = 1’b1   // (3-2=1) =>result = 3’b001;   overflow = 1’b0  

a = 3’b011 b = 3’b010 m = 1’b0     //(3+2=5) =>  result = 3’b101;  overflow =1’b1   Overflow Error!

a = 3’b110 b = 3’b101 m = 1’b0     //(-2-3)=-5) => result = 3’b011; overflow =1’b1   Overflow Error!

Your Testbench should clearly display theinputs and output results

=============full_adder.v====================

//full_adder.v

module full_adder
(
input a,b,ci,
output s, co
);

wire w1, w2, w3;

xor x1(w1, a, b);
xor x2(s, w1, ci);
nand n1(w2, w1, ci);
nand n2(w3, a, b);
nand n3(co, w2, w3);

endmodule