create verilog source files for a seven segment display using the software vivado. show your steps.

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Electrical Engineering

create verilog source files for a seven segmentdisplay using the software vivado.
show your steps.

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module segmant_display7_display(
Â Â Â Â binary_coded_decimal,
Â Â Â Â segmant_display
Â Â Â );
Â Â Â
Â Â Â Â //IO and Variable declarations.
Â Â Â Â input [3:0] binary_coded_decimal;
Â Â Â Â output [6:0] segmant_display;
Â Â Â Â reg [6:0] segmant_display;

Â Â Â always @(binary_coded_decimal)
Â Â Â begin
Â Â Â Â Â Â Â case (binary_coded_decimal) //case statement
Â Â Â Â Â Â Â Â Â Â Â 0 : segmant_display = 7'b0000001;
Â Â Â Â Â Â Â Â Â Â Â 1 : segmant_display = 7'b1001111;
Â Â Â Â Â Â Â Â Â Â Â 2 : segmant_display = 7'b0010010;
Â Â Â Â Â Â Â Â Â Â Â 3 : segmant_display = 7'b0000110;
Â Â Â Â Â Â Â Â Â Â Â 4 : segmant_display = 7'b1001100;
Â Â Â Â Â Â Â Â Â Â Â 5 : segmant_display = 7'b0100100;
Â Â Â Â Â Â Â Â Â Â Â 6 : segmant_display = 7'b0100000;
Â Â Â Â Â Â Â Â Â Â Â 7 : segmant_display = 7'b0001111;
Â Â Â Â Â Â Â Â Â Â Â 8 : segmant_display = 7'b0000000;
Â Â Â Â Â Â Â Â Â Â Â 9 : segmant_display = 7'b0000100;
Â Â Â Â Â Â Â Â Â Â Â default : segmant_display = 7'b1111111;
Â Â Â Â Â Â Â endcase
Â Â Â end
Â Â
endmodule

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