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Consider the SystemVerilog source code shown below. module question 3 (input logic resetn, clock output...

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Consider the SystemVerilog source code shown below. module question 3 (input logic resetn, clock output logic !, g, h); logic (8:0] counter: always_ff @ posedge clock or negedge resetn) if (!reset) begin 11'bo: counter - 9'000000000: end else begin counter c counter + 9'b000000001; if (counter [8:6] -- 3'b101) 11'b: if (counter - 9'b111111111) 1 - 1'bo: end always_comb begin g-1'61 if (counter > 9'd124) 9-1'bo: if (counter - 9'd270) 9-1'b: end assignh - (counter (8:5] -- 4'hB); endmodule Draw one full period for the waves of the periodic signals 5, 9 and from the above code. Consider the clock frequency to be 10 MHz. Show the duration in ns (i.e., nanoseconds) for every interval for level and 1 respectively for f. 9 and h. Although it is not explicitly requested, you can draw other waves, such as the wave for counter, in order to ease the drawing of the waves for f. and

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