code an 8 bit LFSR random number generator in system verilog. Write a test bench, load...

Free

50.1K

Verified Solution

Question

Electrical Engineering

code an 8 bit LFSR random number generator in system verilog.Write a test bench, load the seed 11111111, and generate the first10 random numbers.

Answer & Explanation Solved by verified expert

4.2 Ratings (546 Votes)

module lfsrcode (output reg [7:0]out, input clk, input rst);

wire fdbk;

assign fdbk = ~(out[7] ^ out[6]);

always @(posedge clk, negedge rst)

begin

if (!rst)

out = 8'b11111111;

else

out = {out[6:0],fdbk};

end

endmodule

//testbench//

`timescale 1ns/1ps

module lfsrcode_test();

Â Â Â Â reg clk,rst;

Â Â Â Â wire [7:0]out;

Â Â Â Â Lfsrcode UUT(.out(out),.clk(clk),.rst(rst));

Â Â Â Â initial

Â Â Â Â Â Â Â Â begin

Â Â Â Â Â Â Â Â $display(â€œtime,\t out,â€);

Â Â Â Â Â Â Â Â $monitor(â€œ%g,\t %bâ€,$time,out);
#500 $stop;

Â Â Â Â Â Â Â Â end

Â Â Â Â Â Â Â Â always

Â Â Â Â Â Â Â Â Â Â Â Â begin

Â Â Â Â Â Â Â Â Â Â Â Â #50 clk_tb=1?b1;

Â Â Â Â Â Â Â Â Â Â Â Â #50 clk_tb=1?b0;

Â Â Â Â Â Â Â Â Â Â Â Â end

endmodule

Get Answers to Unlimited Questions

Join us to gain access to millions of questions and expert answers. Enjoy exclusive benefits tailored just for you!

Membership Benefits:

Unlimited Question Access with detailed Answers
Zin AI - 3 Million Words
10 Dall-E 3 Images
20 Plot Generations
Conversation with Dialogue Memory
No Ads, Ever!
Access to Our Best AI Platform: Flex AI - Your personal assistant for all your inquiries!

Become a Member