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Analyze the following Verilog code and write down its output as pictured in the code. module blocking; reg...

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Electrical Engineering

Analyze the following Verilog code and writedown its output as pictured in the code.

module blocking;

reg [0:7] A, B;

initial begin: init1

A = last decimal digit of your ID;

#1 A = A + 1; // blocking procedural assignment

B = A + 1;

$display(\"Output 1: A= %b B= %b\", A, B );

A = last decimal digit of your ID;

#1 A <= A + 1;

B <= A + 1;

#1 $display (\"Output 2: A= %b B= %b\", A, B );

end

endmodule

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