1. A testbench is provided in the following directory(~lab_work/verification/task3) without the Device Under Test(DUT).(see testbench below)

`timescale 1ns/10ps

module tb_detector ;

reg clk, rst, datain;
wire det;

detector DUT ( .clk(clk), .rst(rst), .datain(datain), .det(det));


initial
begin
#0 clk = 0;
datain = 0;
forever #5 clk = ~clk;
end

initial
begin
#0 rst = 0;
@ (negedge clk);
@ (negedge clk);
rst = 1;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;

@(posedge clk)
#2 if (det == 1)
$display (\"det = %b, correct output\", det);
else
$display (\"det = %b, incorrect output\", det);

@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 0;

@(posedge clk)
#2 if (det == 0)
$display (\"det = %b, correct output\", det);
else
$display (\"det = %b, incorrect output\", det);

@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 0;
@ (negedge clk);
datain = 1;
@ (negedge clk);
datain = 1;

@(posedge clk)
#2 if (det == 1)
$display (\"det = %b, correct output\", det);
else
$display (\"det = %b, incorrect output\", det);

@ (negedge clk);
datain = 1;

#100 $finish;
end



endmodule

1. Write a verilog code for the DUT that will dothe following:

i) receive clk, rst dan datain signals from the providedtestbench

ii) reset the output signal to LOW synchronously with thepositive (rising) edge of clk when rst is set LOW

iii) produce an output signal similar to datain when rst is HIGHand the output transition occurs at the negative (falling) edge ofclk.

1. Verify the design using the testbench.