a) i) The following VHDL code contains erroneous syntax. Rewrite the code in its corrected format onto your answer sheet. Youmay assume that din is a 16-bit vector and that the ld, lr and clinputs are 1-bit wide.
lp: process(clk)
signal reg : std_logic_vector(15 downt
begin
if cl=’1’ then
reg := (others:=’0’);
else
if clk=’1’ and clkevent then
if ld=’1’
reg <= din;
end if;
if lr=’1’ then
reg := reg(14 downto 0) & “0
else
reg := ‘0’ && reg(15 downto
end if;
end if;
end process
Describe, in your own words, the functionality of thecircuit
described by the corrected VHDL code from i). Your answer
must explain the purpose of the lr, ld and cl inputs.
