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(a) Design an FSM (only state diagram and state table) for a 3-bit counter that counts...

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Electrical Engineering

(a) Design an FSM (only state diagram and state table) for a3-bit counter that counts through odd numbers downwards. Assume thereset state to be the lowest value of the counter. Use an activelow reset to reset the counter.

(b) Write a behavioral VHDL code that implements the FSM.

(c) Write a VHDL test bench to test the FSM.

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